The following describes two prior art methods for filling patterned openings by electroplating (electrofilling). In accordance with one prior art method, an insulating mask such as an oxide, photoresist, or polyimide layer is patterned over a conductive metallic surface or a “seed layer” (or “plating base”), exposing only the metallic surface at the bottom of the openings. Electroplating is carried out through the openings in the insulating mask, and is confined inside the openings of the mask (for as long as the deposit thickness does not exceed the openings depth). Usually, following the electroplating, the insulating mask is removed, and the unplated seed layer (which was covered by the insulating mask during electroplating) is etched away. This prior art method is often used in fabricating, for example, coils and magnetic poles and other metallic structures of thin film heads, metallic conductors in high density packages (such as flip-chips, chip-scale packaging, and wafer-scale packaging), and in MEMS devices.
In accordance with a second prior art method, sometimes referred to as Damascene or Dual Damascene (DD), an insulating (or dielectric) layer is first pattern-etched to form openings therein. Next, at least one metallic layer is deposited over the insulating layer to metallize its top surface (sometimes referred to as a field), as well as the sidewalls and bottom surfaces of the openings. The metallic layer(s) serves as a conductive plating seed (or plating base) layer, to provide a low resistive electric path for the electroplating current. Electroplating is then carried out over the entire metallized surface, including the field and inside the patterned openings. Following electroplating, the plated metal and any metallization (adhesion, barrier, or seed) layers above the field, as well as any excess plated metal over the openings, are removed by etching, polishing, or by chemical mechanical polishing (CMP). This results in metallic filled vias or trenches (or grooves), embedded in (or surrounded by) a dielectric. This prior art method is used, for example, to produce metallic interconnects in semiconductor integrated circuits devices.
Electroplating often requires a high degree of plated metal thickness uniformity and, in the case of alloy plating, composition uniformity. Uniformity is typically further defined as macro-uniformity (i.e., uniformity over relatively large dimensions of about 1 cm, or larger, such as across a wafer), and micro-uniformity (i.e., uniformity over small dimensions of a few millimeters, or smaller, such as across an individual micro-device or a die). When electroplating an alloy through a patterned mask, such as a photoresist mask, composition non-uniformity is often encountered among opening areas of different aspect ratios. Such micro-non-uniformity is due to insufficient agitation and replenishment of the minor constituent(s) inside deep and narrow opening areas. An example of where such a situation may occur is in electroplating of Ni—Fe (permalloy) through a patterned photoresist mask in the course of manufacturing Thin Film Heads (TFH) or Magnetic Bubbles. In this example, Fe+2 ion concentration in the electrolyte is very low compared with Ni+2 ion concentration, i.e., a ratio between the two (Fe+2/Ni+2) is typically only about 0.015-0.030. In contrast, the composition ratio between Fe and Ni in the deposited permalloy (80% Ni and 20% Fe) is about 0.25. In general, uniformities degrade with increasing substrate dimensions and with decreasing feature size. Larger wafers and smaller devices increase the number of devices per wafer, thereby reducing the processing cost per device. Macro-non-uniformity of the current distribution across a wafer, such as due to radial voltage-drop distribution (“terminal effect”), or edge or corner effects, leads to both thickness and composition (in alloys) macro-non-uniformities.
A rotary (wafer or cathode) cell was disclosed by Grandia et al. in U.S. Pat. No. 4,304,641. That patent advocates nozzles of increasing size and uniformly spaced, or the same sized nozzles with decreasing radial spacing, in order to provide a non-uniform differential radial flow distribution on the wafer-cathode. It provides increasing flow rate along the wafer's radius in order to improve Ni—Fe thickness macro-uniformity. The technique relies on decreasing current efficiency with increasing flow rate, as described by Andricacos et al. in Journal of Electrochemical Society, Vol. 136, No. 6, pp. 1336-1340 (1989). However, in addition to decreasing current efficiency, increasing the flow rate also results in sharp increase of the iron content in the deposited permalloy film, as described by Andricacos et al. In addition, the techniques disclosed in the Grandia patent do not provide improved agitation inside features with high aspect ratio and, therefore, do not improve micro-uniformity. The problem is particularly problematic in areas near the center of the wafer, which receive reduced flow. The rotary cell of the Grandia patent requires a relatively low plating rate (about 0.05 μm/min for Ni—Fe alloy). A rotary jets cell was disclosed by Tzanavaras and Cohen in U.S. Pat. No. 5,421,987 (the '987 patent), incorporated herein by reference. The '987 patent discloses a plating cell incorporating a rotating anode/jet assembly (“RAJA”), producing turbulent high pressure jets flow across a wafer. The RAJA of the '987 patent is assembled in a manner to provide (time-averaged) uniform flow distribution of the jets across a facing wafer surface. The plating cell of the '987 patent facilitates high plating rate with good uniformities. The '987 patent discloses integrated jet nozzles and anode segments in one assembly.
Electrofilling problems become more severe with decreasing lateral (or width) dimension W and increasing aspect ratio (AR) of the openings. Aspect ratio is defined here as a ratio between the depth h of the opening and its smallest lateral dimension W: AR=h/W. For example, in today's most advanced copper filling of trenches and vias in integrated circuit interconnects, the openings may have an aspect ratio as high as 10:1 (h=1.5 μm; W=0.15 μm), and future trench and via openings will likely require W≦0.10-0.13 μm, and AR≧12:1. Reliable, void-free filling of such narrow and high AR openings imposes a great deal of difficulty.
In order to overcome the natural tendency to form voids in electrofilling of narrow openings, commercial electrolytes, such as acidic copper sulfate, usually include proprietary surface active “brightener” and/or “leveler” inhibitor additives. The proprietary additives usually comprise surface active organic compounds with functional groups containing sulfur and/or nitrogen atoms. These compounds adsorb onto growth sites of the depositing metal surface, thereby inhibiting (or suppressing) the metal deposition rate. The relatively stagnant electrolyte inside narrow openings results in poor replenishment and depletion of the inhibitor additive there. This depletion results in reduced inhibition and faster growth inside the openings. Due to better supply of the inhibitor at the top corners of the openings and the field, inhibition is stronger at the top corners and at the field (compared with inside the openings). The reduced inhibition inside narrow openings speeds up the plating rate there (relative to the field), thus facilitating void-free filling (or “superfilling”) of narrow openings with large aspect ratios. The mechanism of superfilling narrow openings, using inhibiting additives, was proposed in several publications. For examples, see an article entitled: “Damascene copper electroplating for chip interconnects”, by P. C. Andricacos, at al. in IBM Journal of Research and Development, Vol. 42(5), pp. 567-574, 1998, and an article entitled: “Copper On-Chip Interconnections”, by P. C. Andricacos in The Electrochemical Society Interface, pp. 31-37, Spring 1999.
In order to achieve void-free “superfilling” of narrow openings, the beneficial effect of inhibition gradients must overcome intrinsic void-forming mechanisms due to (a) higher electric field (and current density) at the top corners of the openings and, (b) decreasing plating rate inside openings, along their depth, due to depletion (and gradient) of the plating ion there.
A common problem with soluble anodes (such as Cu anodes in an acidic copper sulfate electrolyte) is the in-situ generation and release of particles due to uneven anodic dissolution. Low anodic current density (like a weak selective etchant) tends to selectively (faster) dissolve grain boundaries and certain grain orientations, thus leading to anodic surface roughening and particle release. For example, dissolving Cu anodes in acidic cupric sulfate electrolyte often generates in-situ particles. Cu anodes often include other elements, such as phosphorus (P) in order to form an anodic film to reduce the particle generation. The dissolved phosphorus may be incorporated in the deposited Cu film, thereby adversely affecting its electrical and mechanical properties. Also, it takes long periods of pre electrolysis to establish the anodic film. Long periods without plating, or removal of the anode from the electrolyte, cause degradation of the anodic film. To prevent defects due to inclusion of particles in the deposited films, electroplating equipment vendors often place the anode(s) in a porous bag or in a basket or a cup separated from the cathode by a perforated screen or “diffusion plate” (or membrane, or filter). See for example, U.S. Pat. No. 6,126,798 to Reid et al. and U.S. Pat. No. 6,080,291 to Woodruff et al. The perforated screen or filter tend to clog in operation, thus requiring down time for periodic maintenance and cleaning and/or replacement. They also restrict electrolyte circulation around the anode surface, thereby increasing deleterious anodic passivation and polarization and thus limiting the operational plating current (or plating rate). In addition, while preventing larger size particles contamination of the deposited film, they are ineffective in preventing smaller size (sub micron) particles from reaching the cathode.
Other problems involved in prior art rotary cells include erratic and unstable electrical contact to the rotating metallic shaft or pipe, and high rotational friction and electrolyte leaks developing in the rotating seal.
Void-free electrofilling of deep and high aspect ratio openings requires complete wetting by the electrolyte of the exposed metallic surface (or the metallization seed layer) inside the openings. The openings may consist of vias, trenches, or patterned photoresist (or other insulating or dielectric layers). Inadequate wetting (or penetration) by the electrolyte inside very deep and narrow (high aspect ratio) openings results in deleterious electrofilling voids. Such voids may create open circuits or high electrical resistance path, thus impairing the functionality of the device. In addition, electrolyte may be entrapped inside such voids, leading to contamination and corrosion which further impair the long term reliability of the device. Such voids are considered to be unacceptable defects, lowering the manufacturing yield and reliability. They ought to be avoided.
Inadequate electrolyte wetting problems are particularly problematic in relatively wide, but very deep openings. In particular, wetting is difficult inside openings with depth in the range of about 5-100 μm and width in the range of about 5-200 μm. Such openings are frequently used in 3-D wafer packaging (for contacts through the wafer), in chip-scale packaging (CSP), wafer-scale packaging (WSP), TFH, MEMS, and systems on chip (SOC). They are prone to insufficient or inadequate electrolyte wetting. For example, vias of such dimensions in 3-D packaging may require several hours of immersion in the electrolyte, for its complete penetration into the vias to wet and plate the lower sidewalls and bottom of the vias. As the width of the openings decreases, capillary forces become stronger, thus improving the wetting. As a result, narrower openings wet better and faster than wider openings of the same depth. For this reason, wetting problems are less prevalent in submicron openings, used in VLSI and ULSI copper interconnects (having width of about 0.1-0.5 μm and depth of about 0.5-1.5 μm), than in the much wider (≧5 μm) and deeper (≧10 μm) openings encountered in packaging. Passive films, such as native oxides and/or surface contamination of the metallization layer, further exacerbate wetting problems. While they are readily accessible and relatively easy to remove from the top field surface (around the openings), they might be significantly more obstinate and harder to remove inside deep openings.
In light of the above, there is a need to overcome one or more of the above-identified problems.